The SpartanMC Project

Instruction Set

Documents

	Instructionset Manual
	Complete SpartanMC Manual

The SpartanMC uses two register addresses per instruction. The first operand (RD register) is automatically used as the destination of the operation. The instruction set is composd of fixed 18 bit instructions grouped in the 4 types shown below.

R-Type (Register Instructions)	I-Type (Immediate Instructions)
All operation which take two register values and compute a result which is stored back into operand one.	This group includes all operations which take one register value and a constand to carry out an operation.

J-Type (Jump Instructions)	M-Type (Memory Instructions)
This group includes the the jump instruction and two branch instructions. The branch instructions interprets a conditioncode flag register to decide either to branch or not	This group is used for memory access operations. All load and store operations are available as half word (9 bit) or full word (18 bit) operation.

Coding Matrices

Coding Matrices

Mainmatrix Instruction Register Bits IR 17 - 13

IR 17-13	..000	..001	..010	..011	..100	..101	..110	..111
00...	Spezial1	Spezial2	J	JALS	BEQZ	BNEZ	BEQZC	BNEZC
01...	ADDI	MOVI	LHI	SIGEX	ANDI	ORI	XORI	MULI
10...	L9	S9	L18	S18	SLLI	--- *)	SRLI	SRAI
11...	SEQI	SNEI	SLTI	SGTI	SLEI	SGEI	IFADDUI	IFSUBUI

Submatrix SPECIAL 1 Instruction Register Bits IR 4 - 0

IR 4-0	..000	..001	..010	..011	..100	..101	..110	..111
00...	orcc	andcc	--- *)	--- *)	SLL	MOV	SRL	SRA
01...	SEQU	SNEU	SLTU	SGTU	SLEU	SGEU	--- *)	--- *)
10...	--- *)	--- *)	--- *)	--- *)	--- *)	--- *)	CBITS	SBITS
11...	--- *)	--- *)	--- *)	--- *)	--- *)	--- *)	--- *)	NOT

Submatrix SPECIAL 2 Instruction Register Bits IR 4 - 0

IR 4-0	..000	..001	..010	..011	..100	..101	..110	..111
00...	RFE	TRAP	JR	JALR	JRS	JALRS	--- *)	--- *)
01...	--- *)	--- *)	--- *)	--- *)	--- *)	--- *)	--- *)	--- *)
10...	ADD	ADDU	SUB	SUBU	AND	OR	XOR	MUL
11...	SEQ	SNE	SLT	SGT	SLE	SGE	MOVI2S	MOVS2I