The SpartanMC is designd for FPGA usage. Current FPGAs are available with 18 bit memory and arithmetic units. Tipically, 16 bit with 2 additional bits for arbitrary use. The SpartanMC core uses 18 bit instructions and datawidth to fit those structures. Furthermore, the two additional bits enables a more efficient instructionset design.

To get the current release of the SpartanMC SoC-Kit and its toolchain binaries you can use our download section.

Currently we are also working on a public svn repository to offer the latest version of the SoC-Kit.

Generally, our toolchain is developed for GNU Linux operation systems. Since we have written some tools in Java they will run platform independend. If you are able to substitude tools like make the build process will probably run on Windows too.

Toolchain	MS Windows	Linux
Simulator	YES (Java required)	YES
System Builder (jConfig)	YES (Java required)	YES
Build Process (XST, configure and make, shell scripts)	NO	YES
GCC	NO	YES
BinUtils	NO	YES

SpartanMC SoCs were implemented on various FPGA boards. The following table gives a selection of often used evaluation boards and its tested clock frequencies:

Board	FPGA	Tested Frequency
ML507	Virtex 5 XC5VFX70T-FF1136-2	80 MHz
SP601	Spartan 6 XC6SLX16-2CSG324	60 MHz
SP605	Spartan 6 XC6SLX45T-3FGG484	80 MHz

It should be noted that the frequency values not representes the technical maximum for the SpartanMC on this devices. The given values were determined in context of projects and may be influenced by other restricions.

Until now the SpartanMC SoC-Kit is implemented on Xilinx devices only. For porting the SoC-Kit on FPGAs of other vendors an adaption of the verilog code is required. Especially the macros for clock generation and memory blocks (used for registers and main memory) have to be adapted.

In order to provide a port for other FPGA vendors e.g. Altera or Lattice, we currently work on a platform independed version of the SpartanMC (using generic memoy modules).