The SpartanMC is a RISC processor core with the following attributes:
  • Instruction set with fixed 18 bit long instructions.
  • Three stage pipeline with a three port memory for operands. This enables simultaneous read of two operands in OF stage and write access in WB stage.
  • Two address machine. The first operand is automatically used as the destination of the operation. Compare instructions do not alter the source registers, but store their result in a condition code register, which can be used for branches.
  • 16 addressable registers which are stored in an FPGA block memory. The assignment of registers is realized by a sliding window technique. The sliding window gives each procedure or each ISR automatically eight new registers, resulting in very fast function calls and interrupt invocations.
The SpartanMC was designed to fits optimal on modern FPGAs (which is the reason for its uncommon instructions and data width of 18 bit).
Currently, the processor core is tested on Xilinx Spartan 3, Spartan 6, Virtex 5 and Virtex 6 FPGAs.